1. Technical Field
The embodiments herein generally relates to in-circuit emulation and particularly relates to transaction monitoring and obtaining debugging information using a FPGA (Field Programmable Logic Array) in real-time. The embodiments herein more particularly relate to capturing transaction signals based on a BUS transaction sequence and displaying the signals on a waveform viewer.
2. Description of the Related Art
Currently, for the chip vending industry it is unavoidable to perform various tests on integrated circuit chips with different specifications to verify whether the operation of the design is correct or not. Therefore, the quality assessment and test for several products has become a significant issue in the chip vending industry. The chip vendor companies are facing an unprecedented challenge of balancing the design realization time, cost and the product market life.
The transaction monitoring and debugging system of the existing techniques use a single FPGA for providing user logic to implement a device under Test (DUT) as well as for implementing a processing unit. The processing unit generally requires more memory for implementation due to which the memory allocation for user logic is subsided.
Also as all the implementations are done in a single FPGA, the availability of pins in the FPGA for including user logic to implement a DUT (Device under Test) is considerably less. Further the existing techniques require an expensive and a purpose specific hardware for the implementation of the user logic
Hence there exists a need for a transaction monitoring and debugging system which provides adequate memory for user logic implementation. Further there is also a need for a transaction monitoring and debugging system which is less expensive and non-protocol specific. Moreover, there is also a need for a transaction monitoring and debugging system which enables transfer of protocol specific transactions to normal wave form viewers for analysis.
The above mentioned shortcomings, disadvantages and problems are addressed herein and which will be understood by reading and studying the following specification.